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4 megabit (256k x 16) 5-volt only cmos flash memory preliminary features single voltage operation - 5v read - 5v reprogramming fast read access time - 90 ns internal erase/program control sector architecture - one 8k words (16k bytes) boot block with programming lockout - two 8k words (16k bytes) parameter blocks - one 232k words (464k bytes) main memory array block fast sector erase time - 10 seconds word-by-word programming - 50 m s/word hardware data protection data polling for end of program detection low power dissipation - 50 ma active current - 300 m a cmos standby current typical 10,000 write cycles pin configurations pin name function a0 - a17 addresses ce chip enable oe output enable we write enable reset reset i/o0 - i/o15 data inputs/outputs nc no connect the at49f4096 is a 5-volt-only, 4 megabit flash memory organized as 256k words of 16 bits each. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 90 ns with power dissipation of just 275 mw. when deselected, the cmos standby current is less than 300 m a. description (continued) at49f4096 tsop top view type 1 soic (sop) 0569c at49f4096 4-219
(continued) device operation read: the at49f4096 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention. command sequences: when the device is first pow- ered on it will be reset to the read or standby mode de- pending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command se- quences are shown in the command definitions table (i/o8 - i/o15 are dont care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. standard microprocessor write timings are used. the address loca- tions used in the command sequences are not affected by entering the command sequences. block diagram to allow for simple in-system reprogrammability, the at49f4096 does not require high input voltages for pro- gramming. five-volt-only commands determine the read and programming operation of the device. reading data out of the device is similar to reading from an eprom; it has standard ce, oe, and we inputs to avoid bus conten- tion. reprogramming the at49f4096 is performed by first erasing a block of data and then programming on a word- by-word basis. the device is erased by executing the erase command sequence; the device internally controls the erase opera- tion. the memory is divided into three blocks for erase op- erations. there are two 8k word parameter block sections and one sector consisting of the boot block and the main memory array block. the at49f4096 is programmed on a word-by-word basis. the device has the capability to protect the data in the boot block; this feature is enabled by a command se- quence. once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 5.5 volts or less are used. the typical number of program and erase cycles is in excess of 10,000 cycles. the optional 8k word boot block section includes a repro- gramming lock out feature to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. description (continued) reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. by applying a 12v 0.5v input signal to the reset pin the boot block array can be reprogrammed even if the boot block program lock- out feature has been enabled (see boot block program- ming lockout override section). erasure: before a word can be reprogrammed, it must be erased. the erased state of the memory bits is a logical 1. the entire device can be erased at one time by using a 6-byte software code. after the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time needed to erase the whole chip is t ec . 4-220 at49f4096
(continued) chip erase: if the boot block lockout has been en- abled, the chip erase function is disabled; sector erases for the parameter blocks and main memory block will still operate. after the full chip erase the device will return back to read mode. any command during chip erase will be ig- nored. sector erase: as an alternative to a full chip erase, the device is organized into three sectors that can be indi- vidually erased. there are two 8k word parameter block sections and one sector consisting of the boot block and the main memory array block. the sector erase command is a six bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched at the rising edge of we. the sector erase starts after the rising edge of we of the sixth cycle. the erase operation is internally controlled; it will automatically time to completion. when the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued. word programming: once a memory block is erased, it is programmed (to a logical 0) on a word-by- word basis. programming is accomplished via the internal device command register and is a 4 bus cycle operation. the device will automatically generate the required inter- nal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset happens during programming, the data at the location be- ing programmed will be corrupted. please note that a data 0 cannot be programmed back to a 1; only erase opera- tions can convert 0s to 1s. programming is completed after the specified t bp cycle time. the data polling fea- ture may also be used to indicate the end of a program cycle. boot block programming lockout: the de- vice has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 8k words. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout fea- ture will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; the boot blocks usage as a write protected region is optional to the user. the address range of the boot block is 00000h to 01fffh. once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5v or less are used. data in the main memory block can device operation (continued) still be changed through the regular programming method. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the command definitions table. boot block lockout detection: a software method is available to determine if programming of the boot block section is locked out. when the device is in the software product identification mode (see software prod- uct identification entry and exit sections) a read from ad- dress location 00002h will show if programming the boot block is locked out. if the data on i/o0 is low, the boot block can be programmed; if the data on i/o0 is high, the program lockout feature has been enabled and the block cannot be programmed. the software product identifica- tion exit code should be used to return to standard opera- tion. boot block programming lockout over- ride: the user can override the boot block programming lockout by taking the reset pin to 12 volts. by doing this protected boot block data can be altered through a chip erase, sector erase or word programming. when the re - set pin is brought back to ttl levels the boot block pro- gramming lockout feature is again active. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at49f4096 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a 0 on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. toggle bit: in addition to data p o l l i n g t h e at49f4096 provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. at49f4096 4-221
temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* command definition (in hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1addrd out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (4, 5) 30 word program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (2) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (3) 3 5555 aa 2aaa 55 5555 f0 product id exit (3) 1xxxxf0 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex) 2. the 8k word boot sector has the address range 00000h to 01fffh. 3. either one of the product id exit commands can be used. 4. sa = sector addresses: sa = 03xxx for parameter block 1 sa = 05xxx for parameter block 2 sa = 3fxxx for main memory array 5. when the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued. hardware data protection: hardware features protect against inadvertent programs to the at49f4096 in the following ways: (a) v cc sense: if v cc is below 3.8v (typical), the program function is inhibited. (b) v cc power on delay: once v cc has reached the v cc sense level, the device will automat ically time out 10 ms (typical) be- fore programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. device operation (continued) 4-222 at49f4096
operating modes mode ce oe we reset ai i/o read v il v il v ih v ih ai d out program/erase (2) v il v ih v il v ih ai d in standby/write inhibit v ih x (1) xv ih x high z program inhibit x x v ih v ih program inhibit x v il xv ih output disable x v ih xv ih high z reset x x x v il x high z product identification hardware v il v il v ih v ih a1 - a17 = vil, a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a17 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) v ih a0 = vil, a1 - a17 = v il manufacturer code (4) a0 = v ih , a1 - a17 = v il device code (4) 4. manufacturer code: 1fh, device code: 92h 5. see details under software product identification entry/exit. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. dc and ac operating range at49f4096-90 at49f4096-12 operating temperature (case) com. 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 300 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .45 v v oh1 output high voltage i oh = -400 m a 2.4 v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v note: 1. in the erase mode, i cc is 90 ma. at49f4096 4-223
ac read characteristics at49f4096-90 at49f4096-12 symbol parameter min max min max units t acc address to output delay 90 120 ns t ce (1) ce to output delay 90 120 ns t oe (2) oe to output delay 0 40 0 50 ns t df (3, 4) ce or oe to output float 0 25 0 30 ns t oh output hold from oe, ce or address, whichever occurred first 00 ns notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5 ns input test waveforms and measurement level output test load pin capacitance (f = 1 mhz, t = 25c) (1) typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v note: 1. this parameter is characterized and is not 100% tested. 4-224 at49f4096
ac word load characteristics symbol parameter min max units t as , t oes address, oe set-up time 10 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 90 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 10 ns t wph write pulse width high 90 ns ac word load waveforms we controlled ce controlled at49f4096 4-225
program cycle characteristics symbol parameter min max units t bp word programming time 50 m s t as address set-up time 10 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 10 ns t wp write pulse width 90 ns t wph write pulse width high 90 ns t ec erase cycle time 10 seconds program cycle waveforms sector or chip erase cycle waveforms note: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 5555. for sector erase, the address depends on what sector is to be erased. (see note 4 under command definitions.) 3. for chip erase, the data should be 10 h , and for sector erase, the data should be 30 h . 4-226 at49f4096
data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1, 2, 3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. at49f4096 4-227
load data f0 to any address exit product identification mode (4) enter product identification mode (2, 3, 5) load data 90 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes for software product identification: 1. data format: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex) address format: a14 - a0 (hex). 2. a1 - a17 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1fh device code: 92h 6. either one of the product id exit commands can be used. software product identification entry (1) load data f0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 software product identification exit (1, 6) exit product identification mode (4) or load data 80 to address 5555 load data 55 to address 2aaa boot block lockout enable algorithm (1) notes for boot block lockout feature enable: 1. data format: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex) address format: a14 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data aa to address 5555 pause 1 second load data 40 to address 5555 4-228 at49f4096
ordering information (1) t acc (ns) i cc (ma) ordering code package operation range active standby 90 50 0.3 at49f4096-90tc 48t commercial at49f4096-90rc 44r (0 to 70 c) 50 0.3 AT49F4096-90TI 48t industrial at49f4096-90ri 44r (-40 to 85 c) 120 50 0.3 at49f4096-12tc 48t commercial at49f4096-12rc 44r (0 to 70 c) 50 0.3 at49f4096-12ti 48t industrial at49f4096-12ri 44r (-40 to 85 c) note: 1. the at49f4096 has as optional boot block feature. the part number shown in the ordering information table is for devices with the boot block in the lower address range (i.e., 00000h to 01fffh). users requiring the boot block to be in the higher address range should contact atmel. package type 48t 48 lead, thin small outline package (tsop) 44r 44 lead, 0.525" wide, plastic gull wing small outline package (soic) at49f4096 4-229

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